/****************************************************************************
*
* Copyright (c) 2023  C*Core -   All Rights Reserved
*
* THIS SOFTWARE IS DISTRIBUTED "AS IS, " AND ALL WARRANTIES ARE DISCLAIMED,
* INCLUDING MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*
* PROJECT     : CCFC2011BC
* DESCRIPTION : CCFC2011BC adc low level drivers h file
* HISTORY     : Initial version
* @file     adc_lld.h
* @version  1.1
* @date     2023 - 02 - 20
* @brief    Initial version.
*
*****************************************************************************/
#ifndef ADC_LLD_H_
#define ADC_LLD_H_
#include "CCFC2011BC.h"
#include "siul_lld.h"
#include "lldconf.h"

/************************************************************************
* @brief    ADC_0 with 10-bit resolution and ADC_1 with 12-bit resolution
*************************************************************************/
#define ADC0_10BIT          (0x3FFU)
#define ADC1_12BIT          (0xFFFU)

/************************************************************************
* @brief    ADC SIUL PCRnum
*************************************************************************/
/**
* @brief    ADC0_CH0 ~ ADC0_CH15.
**/
#define ADC0_CH0_PCR        (PB4_PCR)       /* PB4 : ADC0_CH0,  ADC1_CH0  */
#define ADC0_CH1_PCR        (PB5_PCR)       /* PB5 : ADC0_CH1,  ADC1_CH1  */
#define ADC0_CH2_PCR        (PB6_PCR)       /* PB6 : ADC0_CH2,  ADC1_CH2  */
#define ADC0_CH3_PCR        (PB7_PCR)       /* PB7 : ADC0_CH3,  ADC1_CH3  */
#define ADC0_CH4_PCR        (PD0_PCR)       /* PD0 : ADC0_CH4,  ADC1_CH4  */
#define ADC0_CH5_PCR        (PD1_PCR)       /* PD1 : ADC0_CH5,  ADC1_CH5  */
#define ADC0_CH6_PCR        (PD2_PCR)       /* PD2 : ADC0_CH6,  ADC1_CH6  */
#define ADC0_CH7_PCR        (PD3_PCR)       /* PD3 : ADC0_CH7,  ADC1_CH7  */
#define ADC0_CH8_PCR        (PD4_PCR)       /* PD4 : ADC0_CH8,  ADC1_CH8  */
#define ADC0_CH9_PCR        (PD5_PCR)       /* PD5 : ADC0_CH9,  ADC1_CH9  */
#define ADC0_CH10_PCR       (PD6_PCR)       /* PD6 : ADC0_CH10, ADC1_CH10 */
#define ADC0_CH11_PCR       (PD7_PCR)       /* PD7 : ADC0_CH11, ADC1_CH11 */
#define ADC0_CH12_PCR       (PD8_PCR)       /* PD8 : ADC0_CH12, ADC1_CH12 */
#define ADC0_CH13_PCR       (PD9_PCR)       /* PD9 : ADC0_CH13, ADC1_CH13 */
#define ADC0_CH14_PCR       (PD10_PCR)      /* PD10: ADC0_CH14, ADC1_CH14 */
#define ADC0_CH15_PCR       (PD11_PCR)      /* PD11: ADC0_CH15, ADC1_CH15 */

/**
* @brief    ADC0_P0 ~ ADC0_P15(ADC0_CH0 ~ ADC0_CH15).
**/
#define ADC0_P0             (ADC0_CH0_PCR)  /* PB4 : ADC0_CH0,  ADC1_CH0  */
#define ADC0_P1             (ADC0_CH1_PCR)  /* PB5 : ADC0_CH1,  ADC1_CH1  */
#define ADC0_P2             (ADC0_CH2_PCR)  /* PB6 : ADC0_CH2,  ADC1_CH2  */
#define ADC0_P3             (ADC0_CH3_PCR)  /* PB7 : ADC0_CH3,  ADC1_CH3  */
#define ADC0_P4             (ADC0_CH4_PCR)  /* PD0 : ADC0_CH4,  ADC1_CH4  */
#define ADC0_P5             (ADC0_CH5_PCR)  /* PD1 : ADC0_CH5,  ADC1_CH5  */
#define ADC0_P6             (ADC0_CH6_PCR)  /* PD2 : ADC0_CH6,  ADC1_CH6  */
#define ADC0_P7             (ADC0_CH7_PCR)  /* PD3 : ADC0_CH7,  ADC1_CH7  */
#define ADC0_P8             (ADC0_CH8_PCR)  /* PD4 : ADC0_CH8,  ADC1_CH8  */
#define ADC0_P9             (ADC0_CH9_PCR)  /* PD5 : ADC0_CH9,  ADC1_CH9  */
#define ADC0_P10            (ADC0_CH10_PCR) /* PD6 : ADC0_CH10, ADC1_CH10 */
#define ADC0_P11            (ADC0_CH11_PCR) /* PD7 : ADC0_CH11, ADC1_CH11 */
#define ADC0_P12            (ADC0_CH12_PCR) /* PD8 : ADC0_CH12, ADC1_CH12 */
#define ADC0_P13            (ADC0_CH13_PCR) /* PD9 : ADC0_CH13, ADC1_CH13 */
#define ADC0_P14            (ADC0_CH14_PCR) /* PD10: ADC0_CH14, ADC1_CH14 */
#define ADC0_P15            (ADC0_CH15_PCR) /* PD11: ADC0_CH15, ADC1_CH15 */

/**
* @brief    ADC1_CH0 ~ ADC1_CH15.
**/
#define ADC1_CH0_PCR        (ADC0_CH0_PCR)  /* PB4 : ADC0_CH0,  ADC1_CH0  */
#define ADC1_CH1_PCR        (ADC0_CH1_PCR)  /* PB5 : ADC0_CH1,  ADC1_CH1  */
#define ADC1_CH2_PCR        (ADC0_CH2_PCR)  /* PB6 : ADC0_CH2,  ADC1_CH2  */
#define ADC1_CH3_PCR        (ADC0_CH3_PCR)  /* PB7 : ADC0_CH3,  ADC1_CH3  */
#define ADC1_CH4_PCR        (ADC0_CH4_PCR)  /* PD0 : ADC0_CH4,  ADC1_CH4  */
#define ADC1_CH5_PCR        (ADC0_CH5_PCR)  /* PD1 : ADC0_CH5,  ADC1_CH5  */
#define ADC1_CH6_PCR        (ADC0_CH6_PCR)  /* PD2 : ADC0_CH6,  ADC1_CH6  */
#define ADC1_CH7_PCR        (ADC0_CH7_PCR)  /* PD3 : ADC0_CH7,  ADC1_CH7  */
#define ADC1_CH8_PCR        (ADC0_CH8_PCR)  /* PD4 : ADC0_CH8,  ADC1_CH8  */
#define ADC1_CH9_PCR        (ADC0_CH9_PCR)  /* PD5 : ADC0_CH9,  ADC1_CH9  */
#define ADC1_CH10_PCR       (ADC0_CH10_PCR) /* PD6 : ADC0_CH10, ADC1_CH10 */
#define ADC1_CH11_PCR       (ADC0_CH11_PCR) /* PD7 : ADC0_CH11, ADC1_CH11 */
#define ADC1_CH12_PCR       (ADC0_CH12_PCR) /* PD8 : ADC0_CH12, ADC1_CH12 */
#define ADC1_CH13_PCR       (ADC0_CH13_PCR) /* PD9 : ADC0_CH13, ADC1_CH13 */
#define ADC1_CH14_PCR       (ADC0_CH14_PCR) /* PD10: ADC0_CH14, ADC1_CH14 */
#define ADC1_CH15_PCR       (ADC0_CH15_PCR) /* PD11: ADC0_CH15, ADC1_CH15 */

/**
* @brief    ADC1_P0 ~ ADC1_P15(ADC1_CH0 ~ ADC1_CH15).
**/
#define ADC1_P0             (ADC1_CH0_PCR)  /* PB4 : ADC0_CH0,  ADC1_CH0  */
#define ADC1_P1             (ADC1_CH1_PCR)  /* PB5 : ADC0_CH1,  ADC1_CH1  */
#define ADC1_P2             (ADC1_CH2_PCR)  /* PB6 : ADC0_CH2,  ADC1_CH2  */
#define ADC1_P3             (ADC1_CH3_PCR)  /* PB7 : ADC0_CH3,  ADC1_CH3  */
#define ADC1_P4             (ADC1_CH4_PCR)  /* PD0 : ADC0_CH4,  ADC1_CH4  */
#define ADC1_P5             (ADC1_CH5_PCR)  /* PD1 : ADC0_CH5,  ADC1_CH5  */
#define ADC1_P6             (ADC1_CH6_PCR)  /* PD2 : ADC0_CH6,  ADC1_CH6  */
#define ADC1_P7             (ADC1_CH7_PCR)  /* PD3 : ADC0_CH7,  ADC1_CH7  */
#define ADC1_P8             (ADC1_CH8_PCR)  /* PD4 : ADC0_CH8,  ADC1_CH8  */
#define ADC1_P9             (ADC1_CH9_PCR)  /* PD5 : ADC0_CH9,  ADC1_CH9  */
#define ADC1_P10            (ADC1_CH10_PCR) /* PD6 : ADC0_CH10, ADC1_CH10 */
#define ADC1_P11            (ADC1_CH11_PCR) /* PD7 : ADC0_CH11, ADC1_CH11 */
#define ADC1_P12            (ADC1_CH12_PCR) /* PD8 : ADC0_CH12, ADC1_CH12 */
#define ADC1_P13            (ADC1_CH13_PCR) /* PD9 : ADC0_CH13, ADC1_CH13 */
#define ADC1_P14            (ADC1_CH14_PCR) /* PD10: ADC0_CH14, ADC1_CH14 */
#define ADC1_P15            (ADC1_CH15_PCR) /* PD11: ADC0_CH15, ADC1_CH15 */

/**
* @brief    ADC0_CH32 ~ ADC0_CH59.
**/
#define ADC0_CH32_PCR       (PB8_PCR)       /* PB8 : ADC0_CH32, ADC1_CH36 */
#define ADC0_CH33_PCR       (PB9_PCR)       /* PB9 : ADC0_CH33, ADC1_CH37 */
#define ADC0_CH34_PCR       (PB10_PCR)      /* PB10: ADC0_CH34, ADC1_CH38 */
#define ADC0_CH35_PCR       (PB11_PCR)      /* PB11: ADC0_CH35 */
#define ADC0_CH36_PCR       (PD12_PCR)      /* PD12: ADC0_CH36 */
#define ADC0_CH37_PCR       (PD13_PCR)      /* PD13: ADC0_CH37 */
#define ADC0_CH38_PCR       (PD14_PCR)      /* PD14: ADC0_CH38 */
#define ADC0_CH39_PCR       (PD15_PCR)      /* PD15: ADC0_CH39 */
#define ADC0_CH40_PCR       (PF0_PCR)       /* PF0 : ADC0_CH40 */
#define ADC0_CH41_PCR       (PF1_PCR)       /* PF1 : ADC0_CH41 */
#define ADC0_CH42_PCR       (PF2_PCR)       /* PF2 : ADC0_CH42 */
#define ADC0_CH43_PCR       (PF3_PCR)       /* PF3 : ADC0_CH43 */
#define ADC0_CH44_PCR       (PF4_PCR)       /* PF4 : ADC0_CH44 */
#define ADC0_CH45_PCR       (PF5_PCR)       /* PF5 : ADC0_CH45 */
#define ADC0_CH46_PCR       (PF6_PCR)       /* PF6 : ADC0_CH46 */
#define ADC0_CH47_PCR       (PF7_PCR)       /* PF7 : ADC0_CH47 */
#define ADC0_CH48_PCR       (PI8_PCR)       /* PI8 : ADC0_CH48 */
#define ADC0_CH49_PCR       (PI9_PCR)       /* PI9 : ADC0_CH49 */
#define ADC0_CH50_PCR       (PI10_PCR)      /* PI10: ADC0_CH50 */
#define ADC0_CH51_PCR       (PI11_PCR)      /* PI11: ADC0_CH51 */
#define ADC0_CH52_PCR       (PI12_PCR)      /* PI12: ADC0_CH52 */
#define ADC0_CH53_PCR       (PI13_PCR)      /* PI13: ADC0_CH53 */
#define ADC0_CH54_PCR       (PI14_PCR)      /* PI14: ADC0_CH54 */
#define ADC0_CH55_PCR       (PI15_PCR)      /* PI15: ADC0_CH55 */
#define ADC0_CH56_PCR       (PJ0_PCR)       /* PJ0 : ADC0_CH56 */
#define ADC0_CH57_PCR       (PJ1_PCR)       /* PJ1 : ADC0_CH57 */
#define ADC0_CH58_PCR       (PJ2_PCR)       /* PJ2 : ADC0_CH58 */
#define ADC0_CH59_PCR       (PJ3_PCR)       /* PJ3 : ADC0_CH59 */

/**
* @brief    ADC0_S0 ~ ADC0_S27(ADC0_CH32 ~ ADC0_CH59).
**/
#define ADC0_S0             (ADC0_CH32_PCR) /* PB8 : ADC0_CH32, ADC1_CH36 */
#define ADC0_S1             (ADC0_CH33_PCR) /* PB9 : ADC0_CH33, ADC1_CH37 */
#define ADC0_S2             (ADC0_CH34_PCR) /* PB10: ADC0_CH34, ADC1_CH38 */
#define ADC0_S3             (ADC0_CH35_PCR) /* PB11: ADC0_CH35 */
#define ADC0_S4             (ADC0_CH36_PCR) /* PD12: ADC0_CH36 */
#define ADC0_S5             (ADC0_CH37_PCR) /* PD13: ADC0_CH37 */
#define ADC0_S6             (ADC0_CH38_PCR) /* PD14: ADC0_CH38 */
#define ADC0_S7             (ADC0_CH39_PCR) /* PD15: ADC0_CH39 */
#define ADC0_S8             (ADC0_CH40_PCR) /* PF0 : ADC0_CH40 */
#define ADC0_S9             (ADC0_CH41_PCR) /* PF1 : ADC0_CH41 */
#define ADC0_S10            (ADC0_CH42_PCR) /* PF2 : ADC0_CH42 */
#define ADC0_S11            (ADC0_CH43_PCR) /* PF3 : ADC0_CH43 */
#define ADC0_S12            (ADC0_CH44_PCR) /* PF4 : ADC0_CH44 */
#define ADC0_S13            (ADC0_CH45_PCR) /* PF5 : ADC0_CH45 */
#define ADC0_S14            (ADC0_CH46_PCR) /* PF6 : ADC0_CH46 */
#define ADC0_S15            (ADC0_CH47_PCR) /* PF7 : ADC0_CH47 */
#define ADC0_S16            (ADC0_CH48_PCR) /* PI8 : ADC0_CH48 */
#define ADC0_S17            (ADC0_CH49_PCR) /* PI9 : ADC0_CH49 */
#define ADC0_S18            (ADC0_CH50_PCR) /* PI10: ADC0_CH50 */
#define ADC0_S19            (ADC0_CH51_PCR) /* PI11: ADC0_CH51 */
#define ADC0_S20            (ADC0_CH52_PCR) /* PI12: ADC0_CH52 */
#define ADC0_S21            (ADC0_CH53_PCR) /* PI13: ADC0_CH53 */
#define ADC0_S22            (ADC0_CH54_PCR) /* PI14: ADC0_CH54 */
#define ADC0_S23            (ADC0_CH55_PCR) /* PI15: ADC0_CH55 */
#define ADC0_S24            (ADC0_CH56_PCR) /* PJ0 : ADC0_CH56 */
#define ADC0_S25            (ADC0_CH57_PCR) /* PJ1 : ADC0_CH57 */
#define ADC0_S26            (ADC0_CH58_PCR) /* PJ2 : ADC0_CH58 */
#define ADC0_S27            (ADC0_CH59_PCR) /* PJ3 : ADC0_CH59 */

/**
* @brief    ADC1_CH32 ~ ADC1_CH39.
**/
#define ADC1_CH32_PCR       (PA3_PCR)       /* PA3 : ADC1_CH32 */
#define ADC1_CH33_PCR       (PA7_PCR)       /* PA7 : ADC1_CH33 */
#define ADC1_CH34_PCR       (PA10_PCR)      /* PA10: ADC1_CH34 */
#define ADC1_CH35_PCR       (PA11_PCR)      /* PA11: ADC1_CH35 */
#define ADC1_CH36_PCR       (ADC0_CH32_PCR) /* PB8 : ADC0_CH32, ADC1_CH36 */
#define ADC1_CH37_PCR       (ADC0_CH33_PCR) /* PB9 : ADC0_CH33, ADC1_CH37 */
#define ADC1_CH38_PCR       (ADC0_CH34_PCR) /* PB10: ADC0_CH34, ADC1_CH38 */
#define ADC1_CH39_PCR       (PE12_PCR)      /* PE12: ADC1_CH39 */

/**
* @brief    ADC1_S0 ~ ADC1_S7(ADC1_CH32 ~ ADC1_CH39).
**/
#define ADC1_S0             (ADC1_CH32_PCR) /* PA3 : ADC1_CH32 */
#define ADC1_S1             (ADC1_CH33_PCR) /* PA7 : ADC1_CH33 */
#define ADC1_S2             (ADC1_CH34_PCR) /* PA10: ADC1_CH34 */
#define ADC1_S3             (ADC1_CH35_PCR) /* PA11: ADC1_CH35 */
#define ADC1_S4             (ADC1_CH36_PCR) /* PB8 : ADC0_CH32, ADC1_CH36 */
#define ADC1_S5             (ADC1_CH37_PCR) /* PB9 : ADC0_CH33, ADC1_CH37 */
#define ADC1_S6             (ADC1_CH38_PCR) /* PB10: ADC0_CH34, ADC1_CH38 */
#define ADC1_S7             (ADC1_CH39_PCR) /* PE12: ADC1_CH39 */

/**
* @brief    ADC0_X[0] ~ ADC0_X[3](ADC0_CH64 ~ ADC0_CH95).
**/
#define ADC0_EX0_PCR        (PB12_PCR)      /* PB12: ADC0_X[0](ADC0_CH64 ~ ADC0_CH71) */
#define ADC0_EX1_PCR        (PB13_PCR)      /* PB13: ADC0_X[1](ADC0_CH72 ~ ADC0_CH79) */
#define ADC0_EX2_PCR        (PB14_PCR)      /* PB14: ADC0_X[2](ADC0_CH80 ~ ADC0_CH87) */
#define ADC0_EX3_PCR        (PB15_PCR)      /* PB15: ADC0_X[3](ADC0_CH88 ~ ADC0_CH95) */

/************************************************************************
* @brief    Main Configuration Register(MCR).
*************************************************************************/
/* Power - down enable */
#define MCR_PWDN_MASK       ((uint32_t)0x00000001UL)
/* Auto - clock - off enable */
#define MCR_ACKO_MASK       ((uint32_t)0x00000020UL)
/* Abort Conversion */
#define MCR_ABORT_MASK      ((uint32_t)0x00000040UL)
/* Abort Chain Conversion */
#define MCR_ABORTCHAIN_MASK ((uint32_t)0x00000080UL)
/* Analog clock select */
#define MCR_ADCLKSEL_MASK   ((uint32_t)0x00000100UL)
/* Cross trigger unit conversion enable */
#define MCR_CTUEN_MASK      ((uint32_t)0x00020000UL)
/* Injection start */
#define MCR_JSTART_MASK     ((uint32_t)0x00100000UL)
/* Injection trigger edge selection */
#define MCR_JEDGE_MASK      ((uint32_t)0x00200000UL)
/* Injection external trigger enable */
#define MCR_JTRGEN_MASK     ((uint32_t)0x00400000UL)
/* Normal Start conversion */
#define MCR_NSTART_MASK     ((uint32_t)0x01000000UL)
/* One Shot/Scan */
#define MCR_MODE_MASK       ((uint32_t)0x20000000UL)
/* Write left/right - aligned */
#define MCR_WLSIDE_MASK     ((uint32_t)0x40000000UL)
/* Overwrite enable */
#define MCR_OWREN_MASK      ((uint32_t)0x80000000UL)

/*
* @brief    MCR_PWDN_MASK.
**/
/* When ADC status is PWDN,
 * resetting this bit starts ADC transition to IDLE mode. */
#define MCR_POWER_IDLE      ((uint32_t)0x00000000UL)
/* When this bit is set,
 * the analog module is requested to enter Power Down mode. */
#define MCR_POWER_DOWN      ((uint32_t)0x00000001UL)  /* Default */

/*
* @brief    MCR_ACKO_MASK.
**/
/* Auto clock off disabled */
#define MCR_ACKOFF_DIS      ((uint32_t)0x00000000UL)
/* Auto clock off enabled */
#define MCR_ACKOFF_EN       ((uint32_t)0x00000020UL)

/*
* @brief    MCR_ABORT_MASK.
**/
#define MCR_ABORT_NULL      ((uint32_t)0x00000000UL)
#define MCR_ABORT_ONGOING   ((uint32_t)0x00000040UL)

/*
* @brief    MCR_ABORTCHAIN_MASK.
**/
#define MCR_ABORTCHAIN_NULL     ((uint32_t)0x00000000UL)
#define MCR_ABORTCHAIN_ONGOING  ((uint32_t)0x00000080UL)

/*
* @brief    MCR_ADCLKSEL_MASK.
* @details  This bit can only be written when ADC in Power - Down mode.
**/
#define MCR_ADCLKSEL_DIV2   ((uint32_t)0x00000000UL)  /* Default */
#define MCR_ADCLKSEL_DIV1   ((uint32_t)0x00000100UL)

/*
* @brief    MCR_CTUEN_MASK.
**/
#define MCR_CTU_DIS         ((uint32_t)0x00000000UL)
#define MCR_CTU_EN          ((uint32_t)0x00020000UL)

/*
* @brief    MCR_JSTART_MASK.
**/
#define MCR_JSTART_NULL     ((uint32_t)0x00000000UL)
#define MCR_JSTART_CONV     ((uint32_t)0x00100000UL)

/*
* @brief    MCR_JEDGE_MASK.
* @details  Edge selection for external trigger, if JTRGEN = 1.
**/
/* Selects falling edge for the external trigger */
#define MCR_JEDGE_FALLING   ((uint32_t)0x00000000UL)
/* Selects rising edge for the external trigger */
#define MCR_JEDGE_RISING    ((uint32_t)0x00200000UL)

/*
* @brief    MCR_JTRGEN_MASK.
**/
#define MCR_JTRGEN_DIS      ((uint32_t)0x00000000UL)
#define MCR_JTRGEN_EN       ((uint32_t)0x00400000UL)

/*
* @brief    MCR_NSTART_MASK.
**/
#define MCR_NSTOP           ((uint32_t)0x00000000UL)
#define MCR_NSTART          ((uint32_t)0x01000000UL)

/*
* @brief    MCR_MODE_MASK.
**/
#define MCR_MODE_ONESHOT    ((uint32_t)0x00000000UL)
#define MCR_MODE_SCAN       ((uint32_t)0x20000000UL)

/*
* @brief    MCR_WLSIDE_MASK.
* @details  The WLSIDE bit affects all the CDR registers simultaneously.
**/
/* The conversion data is written right - aligned */
#define MCR_WLSIDE_RIGHT    ((uint32_t)0x00000000UL)
/* Data is left - aligned (from 15 to (15 - resolution + 1)) */
#define MCR_WLSIDE_LEFT     ((uint32_t)0x40000000UL)

/*
* @brief    MCR_OWREN_MASK.
**/
#define MCR_OWREN_DIS       ((uint32_t)0x00000000UL)
#define MCR_OWREN_EN        ((uint32_t)0x80000000UL)

/************************************************************************
* @brief    Main Status Register(MSR).
*************************************************************************/
#define MSR_ADCSTATUS_MASK  ((uint32_t)0x00000007UL)
#define MSR_ACKO_MASK       ((uint32_t)0x00000020UL)
#define MSR_CHADDR_MASK     ((uint32_t)0x0000FE00UL)
#define MSR_CTUSTART_MASK   ((uint32_t)0x00010000UL)
#define MSR_JSTART_MASK     ((uint32_t)0x00100000UL)
#define MSR_JABORT_MASK     ((uint32_t)0x00800000UL)
#define MSR_NSTART_MASK     ((uint32_t)0x01000000UL)

/************************************************************************
* @brief    Interrupt Status Register (ISR).
* @details  Read  1: interrupt has occurred;
*           Write 1: clear.
*************************************************************************/
/* End of Chain Conversion interrupt flag */
#define ISR_ECH             ((uint32_t)0x00000001UL)
/* End of Channel Conversion interrupt flag */
#define ISR_EOC             ((uint32_t)0x00000002UL)
/* End of Injected Chain Conversion interrupt flag */
#define ISR_JECH            ((uint32_t)0x00000004UL)
/* End of Injected Channel Conversion interrupt flag */
#define ISR_JEOC            ((uint32_t)0x00000008UL)
/* End of CTU Conversion interrupt flag */
#define ISR_EOCTU           ((uint32_t)0x00000010UL)

/************************************************************************
* @brief    Channel Pending Registers 0 (CEOCFR[0]).
* @details  ADC_0 /ADC_1:
*           End of conversion pending interrupt
*           for channel 0 to 15 (precision channels).
*************************************************************************/
#define CEOCFR0_EOC_CH0     ((uint32_t)0x00000001UL)
#define CEOCFR0_EOC_CH1     ((uint32_t)0x00000002UL)
#define CEOCFR0_EOC_CH2     ((uint32_t)0x00000004UL)
#define CEOCFR0_EOC_CH3     ((uint32_t)0x00000008UL)
#define CEOCFR0_EOC_CH4     ((uint32_t)0x00000010UL)
#define CEOCFR0_EOC_CH5     ((uint32_t)0x00000020UL)
#define CEOCFR0_EOC_CH6     ((uint32_t)0x00000040UL)
#define CEOCFR0_EOC_CH7     ((uint32_t)0x00000080UL)
#define CEOCFR0_EOC_CH8     ((uint32_t)0x00000100UL)
#define CEOCFR0_EOC_CH9     ((uint32_t)0x00000200UL)
#define CEOCFR0_EOC_CH10    ((uint32_t)0x00000400UL)
#define CEOCFR0_EOC_CH11    ((uint32_t)0x00000800UL)
#define CEOCFR0_EOC_CH12    ((uint32_t)0x00001000UL)
#define CEOCFR0_EOC_CH13    ((uint32_t)0x00002000UL)
#define CEOCFR0_EOC_CH14    ((uint32_t)0x00004000UL)
#define CEOCFR0_EOC_CH15    ((uint32_t)0x00008000UL)

/************************************************************************
* @brief    Channel Pending Registers 1 (CEOCFR[1]).
* @details  ADC_0:
*           End of conversion pending interrupt
*           for channel 32 to 59 (standard channels).
* @details  ADC_1:
*           End of conversion pending interrupt
*           for channel 32 to 39 (standard channels).
*************************************************************************/
#define CEOCFR1_EOC_CH32    ((uint32_t)0x00000001UL)
#define CEOCFR1_EOC_CH33    ((uint32_t)0x00000002UL)
#define CEOCFR1_EOC_CH34    ((uint32_t)0x00000004UL)
#define CEOCFR1_EOC_CH35    ((uint32_t)0x00000008UL)
#define CEOCFR1_EOC_CH36    ((uint32_t)0x00000010UL)
#define CEOCFR1_EOC_CH37    ((uint32_t)0x00000020UL)
#define CEOCFR1_EOC_CH38    ((uint32_t)0x00000040UL)
#define CEOCFR1_EOC_CH39    ((uint32_t)0x00000080UL)    /* ADC_1 End */
#define CEOCFR1_EOC_CH40    ((uint32_t)0x00000100UL)
#define CEOCFR1_EOC_CH41    ((uint32_t)0x00000200UL)
#define CEOCFR1_EOC_CH42    ((uint32_t)0x00000400UL)
#define CEOCFR1_EOC_CH43    ((uint32_t)0x00000800UL)
#define CEOCFR1_EOC_CH44    ((uint32_t)0x00001000UL)
#define CEOCFR1_EOC_CH45    ((uint32_t)0x00002000UL)
#define CEOCFR1_EOC_CH46    ((uint32_t)0x00004000UL)
#define CEOCFR1_EOC_CH47    ((uint32_t)0x00008000UL)
#define CEOCFR1_EOC_CH48    ((uint32_t)0x00010000UL)
#define CEOCFR1_EOC_CH49    ((uint32_t)0x00020000UL)
#define CEOCFR1_EOC_CH50    ((uint32_t)0x00040000UL)
#define CEOCFR1_EOC_CH51    ((uint32_t)0x00080000UL)
#define CEOCFR1_EOC_CH52    ((uint32_t)0x00100000UL)
#define CEOCFR1_EOC_CH53    ((uint32_t)0x00200000UL)
#define CEOCFR1_EOC_CH54    ((uint32_t)0x00400000UL)
#define CEOCFR1_EOC_CH55    ((uint32_t)0x00800000UL)
#define CEOCFR1_EOC_CH56    ((uint32_t)0x01000000UL)
#define CEOCFR1_EOC_CH57    ((uint32_t)0x02000000UL)
#define CEOCFR1_EOC_CH58    ((uint32_t)0x04000000UL)
#define CEOCFR1_EOC_CH59    ((uint32_t)0x08000000UL)    /* ADC_0 End */

/************************************************************************
* @brief    Channel Pending Registers 2 (CEOCFR[2]).
* @details  ADC_0:
*           End of conversion pending interrupt
*           for channel 64 to 95 (external multiplexed channels).
*************************************************************************/
#define CEOCFR2_EOC_CH64    ((uint32_t)0x00000001UL)
#define CEOCFR2_EOC_CH65    ((uint32_t)0x00000002UL)
#define CEOCFR2_EOC_CH66    ((uint32_t)0x00000004UL)
#define CEOCFR2_EOC_CH67    ((uint32_t)0x00000008UL)
#define CEOCFR2_EOC_CH68    ((uint32_t)0x00000010UL)
#define CEOCFR2_EOC_CH69    ((uint32_t)0x00000020UL)
#define CEOCFR2_EOC_CH70    ((uint32_t)0x00000040UL)
#define CEOCFR2_EOC_CH71    ((uint32_t)0x00000080UL)
#define CEOCFR2_EOC_CH72    ((uint32_t)0x00000100UL)
#define CEOCFR2_EOC_CH73    ((uint32_t)0x00000200UL)
#define CEOCFR2_EOC_CH74    ((uint32_t)0x00000400UL)
#define CEOCFR2_EOC_CH75    ((uint32_t)0x00000800UL)
#define CEOCFR2_EOC_CH76    ((uint32_t)0x00001000UL)
#define CEOCFR2_EOC_CH77    ((uint32_t)0x00002000UL)
#define CEOCFR2_EOC_CH78    ((uint32_t)0x00004000UL)
#define CEOCFR2_EOC_CH79    ((uint32_t)0x00008000UL)
#define CEOCFR2_EOC_CH80    ((uint32_t)0x00010000UL)
#define CEOCFR2_EOC_CH81    ((uint32_t)0x00020000UL)
#define CEOCFR2_EOC_CH82    ((uint32_t)0x00040000UL)
#define CEOCFR2_EOC_CH83    ((uint32_t)0x00080000UL)
#define CEOCFR2_EOC_CH84    ((uint32_t)0x00100000UL)
#define CEOCFR2_EOC_CH85    ((uint32_t)0x00200000UL)
#define CEOCFR2_EOC_CH86    ((uint32_t)0x00400000UL)
#define CEOCFR2_EOC_CH87    ((uint32_t)0x00800000UL)
#define CEOCFR2_EOC_CH88    ((uint32_t)0x01000000UL)
#define CEOCFR2_EOC_CH89    ((uint32_t)0x02000000UL)
#define CEOCFR2_EOC_CH90    ((uint32_t)0x04000000UL)
#define CEOCFR2_EOC_CH91    ((uint32_t)0x08000000UL)
#define CEOCFR2_EOC_CH92    ((uint32_t)0x10000000UL)
#define CEOCFR2_EOC_CH93    ((uint32_t)0x20000000UL)
#define CEOCFR2_EOC_CH94    ((uint32_t)0x40000000UL)
#define CEOCFR2_EOC_CH95    ((uint32_t)0x80000000UL)

/************************************************************************
* @brief    Interrupt Mask Register (IMR).
* @details  Write 1: interrupt is enabled.
*************************************************************************/
/* Mask for end of chain conversion(ECH) interrupt */
#define IMR_MASK_ECH        ((uint32_t)0x00000001UL)
/* Mask for end of channel conversion(EOC) interrupt */
#define IMR_MASK_EOC        ((uint32_t)0x00000002UL)
/* Mask for end of injected chain conversion(JECH) interrupt */
#define IMR_MASK_JECH       ((uint32_t)0x00000004UL)
/* Mask for end of injected channel conversion(JEOC) interrupt */
#define IMR_MASK_JEOC       ((uint32_t)0x00000008UL)
/* Mask for end of CTU conversion(EOCTU) interrupt */
#define IMR_MASK_EOCTU      ((uint32_t)0x00000010UL)

/************************************************************************
* @brief    Channel Interrupt Mask Registers 0 (CIMR[0]).
* @details  ADC_0 /ADC_1:
*           Enable bit for channel 0 to 15 (precision channels).
*************************************************************************/
#define CIMR0_CH0           ((uint32_t)0x00000001UL)
#define CIMR0_CH1           ((uint32_t)0x00000002UL)
#define CIMR0_CH2           ((uint32_t)0x00000004UL)
#define CIMR0_CH3           ((uint32_t)0x00000008UL)
#define CIMR0_CH4           ((uint32_t)0x00000010UL)
#define CIMR0_CH5           ((uint32_t)0x00000020UL)
#define CIMR0_CH6           ((uint32_t)0x00000040UL)
#define CIMR0_CH7           ((uint32_t)0x00000080UL)
#define CIMR0_CH8           ((uint32_t)0x00000100UL)
#define CIMR0_CH9           ((uint32_t)0x00000200UL)
#define CIMR0_CH10          ((uint32_t)0x00000400UL)
#define CIMR0_CH11          ((uint32_t)0x00000800UL)
#define CIMR0_CH12          ((uint32_t)0x00001000UL)
#define CIMR0_CH13          ((uint32_t)0x00002000UL)
#define CIMR0_CH14          ((uint32_t)0x00004000UL)
#define CIMR0_CH15          ((uint32_t)0x00008000UL)

/************************************************************************
* @brief    Channel Interrupt Mask Registers 1 (CIMR[1]).
* @details  ADC_0:
*           Enable bit for channel 32 to 59 (standard channels).
* @details  ADC_1:
*           Enable bit for channel 32 to 39 (standard channels).
*************************************************************************/
#define CIMR1_CH32          ((uint32_t)0x00000001UL)
#define CIMR1_CH33          ((uint32_t)0x00000002UL)
#define CIMR1_CH34          ((uint32_t)0x00000004UL)
#define CIMR1_CH35          ((uint32_t)0x00000008UL)
#define CIMR1_CH36          ((uint32_t)0x00000010UL)
#define CIMR1_CH37          ((uint32_t)0x00000020UL)
#define CIMR1_CH38          ((uint32_t)0x00000040UL)
#define CIMR1_CH39          ((uint32_t)0x00000080UL)    /* ADC_1 End */
#define CIMR1_CH40          ((uint32_t)0x00000100UL)
#define CIMR1_CH41          ((uint32_t)0x00000200UL)
#define CIMR1_CH42          ((uint32_t)0x00000400UL)
#define CIMR1_CH43          ((uint32_t)0x00000800UL)
#define CIMR1_CH44          ((uint32_t)0x00001000UL)
#define CIMR1_CH45          ((uint32_t)0x00002000UL)
#define CIMR1_CH46          ((uint32_t)0x00004000UL)
#define CIMR1_CH47          ((uint32_t)0x00008000UL)
#define CIMR1_CH48          ((uint32_t)0x00010000UL)
#define CIMR1_CH49          ((uint32_t)0x00020000UL)
#define CIMR1_CH50          ((uint32_t)0x00040000UL)
#define CIMR1_CH51          ((uint32_t)0x00080000UL)
#define CIMR1_CH52          ((uint32_t)0x00100000UL)
#define CIMR1_CH53          ((uint32_t)0x00200000UL)
#define CIMR1_CH54          ((uint32_t)0x00400000UL)
#define CIMR1_CH55          ((uint32_t)0x00800000UL)
#define CIMR1_CH56          ((uint32_t)0x01000000UL)
#define CIMR1_CH57          ((uint32_t)0x02000000UL)
#define CIMR1_CH58          ((uint32_t)0x04000000UL)
#define CIMR1_CH59          ((uint32_t)0x08000000UL)    /* ADC_0 End */

/***************************************************************************
* @brief    Channel Interrupt Mask Registers 2 (CIMR[2]).
* @details  ADC_0:
*           Enable bit for channel 64 to 95 (external multiplexed channels).
****************************************************************************/
#define CIMR2_CH64          ((uint32_t)0x00000001UL)
#define CIMR2_CH65          ((uint32_t)0x00000002UL)
#define CIMR2_CH66          ((uint32_t)0x00000004UL)
#define CIMR2_CH67          ((uint32_t)0x00000008UL)
#define CIMR2_CH68          ((uint32_t)0x00000010UL)
#define CIMR2_CH69          ((uint32_t)0x00000020UL)
#define CIMR2_CH70          ((uint32_t)0x00000040UL)
#define CIMR2_CH71          ((uint32_t)0x00000080UL)
#define CIMR2_CH72          ((uint32_t)0x00000100UL)
#define CIMR2_CH73          ((uint32_t)0x00000200UL)
#define CIMR2_CH74          ((uint32_t)0x00000400UL)
#define CIMR2_CH75          ((uint32_t)0x00000800UL)
#define CIMR2_CH76          ((uint32_t)0x00001000UL)
#define CIMR2_CH77          ((uint32_t)0x00002000UL)
#define CIMR2_CH78          ((uint32_t)0x00004000UL)
#define CIMR2_CH79          ((uint32_t)0x00008000UL)
#define CIMR2_CH80          ((uint32_t)0x00010000UL)
#define CIMR2_CH81          ((uint32_t)0x00020000UL)
#define CIMR2_CH82          ((uint32_t)0x00040000UL)
#define CIMR2_CH83          ((uint32_t)0x00080000UL)
#define CIMR2_CH84          ((uint32_t)0x00100000UL)
#define CIMR2_CH85          ((uint32_t)0x00200000UL)
#define CIMR2_CH86          ((uint32_t)0x00400000UL)
#define CIMR2_CH87          ((uint32_t)0x00800000UL)
#define CIMR2_CH88          ((uint32_t)0x01000000UL)
#define CIMR2_CH89          ((uint32_t)0x02000000UL)
#define CIMR2_CH90          ((uint32_t)0x04000000UL)
#define CIMR2_CH91          ((uint32_t)0x08000000UL)
#define CIMR2_CH92          ((uint32_t)0x10000000UL)
#define CIMR2_CH93          ((uint32_t)0x20000000UL)
#define CIMR2_CH94          ((uint32_t)0x40000000UL)
#define CIMR2_CH95          ((uint32_t)0x80000000UL)

/************************************************************************
* @brief    Watchdog Threshold Interrupt Status Register (WTISR).
* @details  Write 1 to clear.
*************************************************************************/
#define ADC_WDG0L           ((uint32_t)0x00000001UL)
#define ADC_WDG0H           ((uint32_t)0x00000002UL)
#define ADC_WDG1L           ((uint32_t)0x00000004UL)
#define ADC_WDG1H           ((uint32_t)0x00000008UL)
#define ADC_WDG2L           ((uint32_t)0x00000010UL)
#define ADC_WDG2H           ((uint32_t)0x00000020UL)    /* ADC_1 End */
#define ADC_WDG3L           ((uint32_t)0x00000040UL)
#define ADC_WDG3H           ((uint32_t)0x00000080UL)
#define ADC_WDG4L           ((uint32_t)0x00000100UL)
#define ADC_WDG4H           ((uint32_t)0x00000200UL)
#define ADC_WDG5L           ((uint32_t)0x00000400UL)
#define ADC_WDG5H           ((uint32_t)0x00000800UL)

/************************************************************************
* @brief    Watchdog Threshold Interrupt Mask Register (WTIMR).
* @details  When set the interrupt is enabled.
*************************************************************************/
#define ADC_MASK_WDG0L      ((uint32_t)0x00000001UL)
#define ADC_MASK_WDG0H      ((uint32_t)0x00000002UL)
#define ADC_MASK_WDG1L      ((uint32_t)0x00000004UL)
#define ADC_MASK_WDG1H      ((uint32_t)0x00000008UL)
#define ADC_MASK_WDG2L      ((uint32_t)0x00000010UL)
#define ADC_MASK_WDG2H      ((uint32_t)0x00000020UL)    /* ADC_1 End */
#define ADC_MASK_WDG3L      ((uint32_t)0x00000040UL)
#define ADC_MASK_WDG3H      ((uint32_t)0x00000080UL)
#define ADC_MASK_WDG4L      ((uint32_t)0x00000100UL)
#define ADC_MASK_WDG4H      ((uint32_t)0x00000200UL)
#define ADC_MASK_WDG5L      ((uint32_t)0x00000400UL)
#define ADC_MASK_WDG5H      ((uint32_t)0x00000800UL)

/************************************************************************
* @brief    DMA Enable Register (DMAE).
*************************************************************************/
/* DMA global enable */
#define ADC_DMAEN           ((uint32_t)0x00000001UL)
/* DMA clear sequence enable */
#define ADC_DCLR            ((uint32_t)0x00000002UL)

/************************************************************************
* @brief    DMA Channel Select Register 0 (DMAR[0]).
* @details  ADC_0 /ADC_1:
*           Enable bit for channel 0 to 15 (precision channels).
*************************************************************************/
#define DMAR0_CH0           ((uint32_t)0x00000001UL)
#define DMAR0_CH1           ((uint32_t)0x00000002UL)
#define DMAR0_CH2           ((uint32_t)0x00000004UL)
#define DMAR0_CH3           ((uint32_t)0x00000008UL)
#define DMAR0_CH4           ((uint32_t)0x00000010UL)
#define DMAR0_CH5           ((uint32_t)0x00000020UL)
#define DMAR0_CH6           ((uint32_t)0x00000040UL)
#define DMAR0_CH7           ((uint32_t)0x00000080UL)
#define DMAR0_CH8           ((uint32_t)0x00000100UL)
#define DMAR0_CH9           ((uint32_t)0x00000200UL)
#define DMAR0_CH10          ((uint32_t)0x00000400UL)
#define DMAR0_CH11          ((uint32_t)0x00000800UL)
#define DMAR0_CH12          ((uint32_t)0x00001000UL)
#define DMAR0_CH13          ((uint32_t)0x00002000UL)
#define DMAR0_CH14          ((uint32_t)0x00004000UL)
#define DMAR0_CH15          ((uint32_t)0x00008000UL)

/************************************************************************
* @brief    DMA Channel Select Register 1 (DMAR[1]).
* @details  ADC_0:
*           Enable bit for channel 32 to 59 (standard channels).
* @details  ADC_1:
*           Enable bit for channel 32 to 39 (standard channels).
*************************************************************************/
#define DMAR1_CH32          ((uint32_t)0x00000001UL)
#define DMAR1_CH33          ((uint32_t)0x00000002UL)
#define DMAR1_CH34          ((uint32_t)0x00000004UL)
#define DMAR1_CH35          ((uint32_t)0x00000008UL)
#define DMAR1_CH36          ((uint32_t)0x00000010UL)
#define DMAR1_CH37          ((uint32_t)0x00000020UL)
#define DMAR1_CH38          ((uint32_t)0x00000040UL)
#define DMAR1_CH39          ((uint32_t)0x00000080UL)    /* ADC_1 End */
#define DMAR1_CH40          ((uint32_t)0x00000100UL)
#define DMAR1_CH41          ((uint32_t)0x00000200UL)
#define DMAR1_CH42          ((uint32_t)0x00000400UL)
#define DMAR1_CH43          ((uint32_t)0x00000800UL)
#define DMAR1_CH44          ((uint32_t)0x00001000UL)
#define DMAR1_CH45          ((uint32_t)0x00002000UL)
#define DMAR1_CH46          ((uint32_t)0x00004000UL)
#define DMAR1_CH47          ((uint32_t)0x00008000UL)
#define DMAR1_CH48          ((uint32_t)0x00010000UL)
#define DMAR1_CH49          ((uint32_t)0x00020000UL)
#define DMAR1_CH50          ((uint32_t)0x00040000UL)
#define DMAR1_CH51          ((uint32_t)0x00080000UL)
#define DMAR1_CH52          ((uint32_t)0x00100000UL)
#define DMAR1_CH53          ((uint32_t)0x00200000UL)
#define DMAR1_CH54          ((uint32_t)0x00400000UL)
#define DMAR1_CH55          ((uint32_t)0x00800000UL)
#define DMAR1_CH56          ((uint32_t)0x01000000UL)
#define DMAR1_CH57          ((uint32_t)0x02000000UL)
#define DMAR1_CH58          ((uint32_t)0x04000000UL)
#define DMAR1_CH59          ((uint32_t)0x08000000UL)    /* ADC_0 End */

/***************************************************************************
* @brief    DMA Channel Select Register 2 (DMAR[2]).
* @details  ADC_0:
*           Enable bit for channel 64 to 95 (external multiplexed channels).
****************************************************************************/
#define DMAR2_CH64          ((uint32_t)0x00000001UL)
#define DMAR2_CH65          ((uint32_t)0x00000002UL)
#define DMAR2_CH66          ((uint32_t)0x00000004UL)
#define DMAR2_CH67          ((uint32_t)0x00000008UL)
#define DMAR2_CH68          ((uint32_t)0x00000010UL)
#define DMAR2_CH69          ((uint32_t)0x00000020UL)
#define DMAR2_CH70          ((uint32_t)0x00000040UL)
#define DMAR2_CH71          ((uint32_t)0x00000080UL)
#define DMAR2_CH72          ((uint32_t)0x00000100UL)
#define DMAR2_CH73          ((uint32_t)0x00000200UL)
#define DMAR2_CH74          ((uint32_t)0x00000400UL)
#define DMAR2_CH75          ((uint32_t)0x00000800UL)
#define DMAR2_CH76          ((uint32_t)0x00001000UL)
#define DMAR2_CH77          ((uint32_t)0x00002000UL)
#define DMAR2_CH78          ((uint32_t)0x00004000UL)
#define DMAR2_CH79          ((uint32_t)0x00008000UL)
#define DMAR2_CH80          ((uint32_t)0x00010000UL)
#define DMAR2_CH81          ((uint32_t)0x00020000UL)
#define DMAR2_CH82          ((uint32_t)0x00040000UL)
#define DMAR2_CH83          ((uint32_t)0x00080000UL)
#define DMAR2_CH84          ((uint32_t)0x00100000UL)
#define DMAR2_CH85          ((uint32_t)0x00200000UL)
#define DMAR2_CH86          ((uint32_t)0x00400000UL)
#define DMAR2_CH87          ((uint32_t)0x00800000UL)
#define DMAR2_CH88          ((uint32_t)0x01000000UL)
#define DMAR2_CH89          ((uint32_t)0x02000000UL)
#define DMAR2_CH90          ((uint32_t)0x04000000UL)
#define DMAR2_CH91          ((uint32_t)0x08000000UL)
#define DMAR2_CH92          ((uint32_t)0x10000000UL)
#define DMAR2_CH93          ((uint32_t)0x20000000UL)
#define DMAR2_CH94          ((uint32_t)0x40000000UL)
#define DMAR2_CH95          ((uint32_t)0x80000000UL)

/************************************************************************
* @brief    Threshold Register (THRHLR).
* @details  ADC_0: THRHLR[0..5].
*           ADC_1: THRHLR[0..2].
*************************************************************************/
#define ADC0_THRHLR_MAX_NUM (4U)
#define ADC1_THRHLR_MAX_NUM (0U)

#define ADC0_THRL_MASK      ((uint32_t)0x000003FFUL)
#define ADC0_THRH_MASK      ((uint32_t)0x03FF0000UL)
#define ADC1_THRL_MASK      ((uint32_t)0x00000FFFUL)
#define ADC1_THRH_MASK      ((uint32_t)0x0FFF0000UL)

/************************************************************************
* @brief    Presampling Control Register (PSCR).
*************************************************************************/
/* Convert presampled value.
 * If bit PRECONV is set, presampling is followed by the conversion.
 * Sampling will be bypassed and conversion of presampled data will be done. */
#define PSCR_PRECONV        ((uint32_t)0x00000001UL)
/* Internal voltage selection for presampling */
/* Selects analog input voltage for presampling from
 * the available two internal voltages (precision channels).*/
#define PSCR_PREVAL0_MASK   ((uint32_t)0x00000006UL)
/* Selects analog input voltage for presampling from
 * the available two internal voltages (standard channels).*/
#define PSCR_PREVAL1_MASK   ((uint32_t)0x00000018UL)
/* Selects analog input voltage for presampling from
 * the available two internal voltages (external multiplexed channels).*/
#define PSCR_PREVAL2_MASK   ((uint32_t)0x00000060UL)

/******************************************************************************
* @brief    Presampling Register 0 (PSR[0]).
* @details  ADC_0 /ADC_1:
*           Enable bit of presampling for channel 0 to 15 (precision channels).
*           Presampling enable,
*           When set (= 1), presampling is enabled for channel n.
*******************************************************************************/
#define PSR0_CH0            ((uint32_t)0x00000001UL)
#define PSR0_CH1            ((uint32_t)0x00000002UL)
#define PSR0_CH2            ((uint32_t)0x00000004UL)
#define PSR0_CH3            ((uint32_t)0x00000008UL)
#define PSR0_CH4            ((uint32_t)0x00000010UL)
#define PSR0_CH5            ((uint32_t)0x00000020UL)
#define PSR0_CH6            ((uint32_t)0x00000040UL)
#define PSR0_CH7            ((uint32_t)0x00000080UL)
#define PSR0_CH8            ((uint32_t)0x00000100UL)
#define PSR0_CH9            ((uint32_t)0x00000200UL)
#define PSR0_CH10           ((uint32_t)0x00000400UL)
#define PSR0_CH11           ((uint32_t)0x00000800UL)
#define PSR0_CH12           ((uint32_t)0x00001000UL)
#define PSR0_CH13           ((uint32_t)0x00002000UL)
#define PSR0_CH14           ((uint32_t)0x00004000UL)
#define PSR0_CH15           ((uint32_t)0x00008000UL)

/******************************************************************************
* @brief    Presampling Register 1 (PSR[1]).
* @details  ADC_0:
*           Enable bit of presampling for channel 32 to 59 (standard channels).
* @details  ADC_1:
*           Enable bit of presampling for channel 32 to 39 (standard channels).
*           Presampling enable,
*           When set (= 1), presampling is enabled for channel n.
*******************************************************************************/
#define PSR1_CH32           ((uint32_t)0x00000001UL)
#define PSR1_CH33           ((uint32_t)0x00000002UL)
#define PSR1_CH34           ((uint32_t)0x00000004UL)
#define PSR1_CH35           ((uint32_t)0x00000008UL)
#define PSR1_CH36           ((uint32_t)0x00000010UL)
#define PSR1_CH37           ((uint32_t)0x00000020UL)
#define PSR1_CH38           ((uint32_t)0x00000040UL)
#define PSR1_CH39           ((uint32_t)0x00000080UL)    /* ADC_1 End */
#define PSR1_CH40           ((uint32_t)0x00000100UL)
#define PSR1_CH41           ((uint32_t)0x00000200UL)
#define PSR1_CH42           ((uint32_t)0x00000400UL)
#define PSR1_CH43           ((uint32_t)0x00000800UL)
#define PSR1_CH44           ((uint32_t)0x00001000UL)
#define PSR1_CH45           ((uint32_t)0x00002000UL)
#define PSR1_CH46           ((uint32_t)0x00004000UL)
#define PSR1_CH47           ((uint32_t)0x00008000UL)
#define PSR1_CH48           ((uint32_t)0x00010000UL)
#define PSR1_CH49           ((uint32_t)0x00020000UL)
#define PSR1_CH50           ((uint32_t)0x00040000UL)
#define PSR1_CH51           ((uint32_t)0x00080000UL)
#define PSR1_CH52           ((uint32_t)0x00100000UL)
#define PSR1_CH53           ((uint32_t)0x00200000UL)
#define PSR1_CH54           ((uint32_t)0x00400000UL)
#define PSR1_CH55           ((uint32_t)0x00800000UL)
#define PSR1_CH56           ((uint32_t)0x01000000UL)
#define PSR1_CH57           ((uint32_t)0x02000000UL)
#define PSR1_CH58           ((uint32_t)0x04000000UL)
#define PSR1_CH59           ((uint32_t)0x08000000UL)    /* ADC_0 End */

/************************************************************************
* @brief    Presampling Register 2 (PSR[2]).
* @details  ADC_0:
*           Enable bit of presampling for channel 64 to 95
*           (external multiplexed channels).
*           Presampling enable,
*           When set (= 1), presampling is enabled for channel n.
*************************************************************************/
#define PSR2_CH64           ((uint32_t)0x00000001UL)
#define PSR2_CH65           ((uint32_t)0x00000002UL)
#define PSR2_CH66           ((uint32_t)0x00000004UL)
#define PSR2_CH67           ((uint32_t)0x00000008UL)
#define PSR2_CH68           ((uint32_t)0x00000010UL)
#define PSR2_CH69           ((uint32_t)0x00000020UL)
#define PSR2_CH70           ((uint32_t)0x00000040UL)
#define PSR2_CH71           ((uint32_t)0x00000080UL)
#define PSR2_CH72           ((uint32_t)0x00000100UL)
#define PSR2_CH73           ((uint32_t)0x00000200UL)
#define PSR2_CH74           ((uint32_t)0x00000400UL)
#define PSR2_CH75           ((uint32_t)0x00000800UL)
#define PSR2_CH76           ((uint32_t)0x00001000UL)
#define PSR2_CH77           ((uint32_t)0x00002000UL)
#define PSR2_CH78           ((uint32_t)0x00004000UL)
#define PSR2_CH79           ((uint32_t)0x00008000UL)
#define PSR2_CH80           ((uint32_t)0x00010000UL)
#define PSR2_CH81           ((uint32_t)0x00020000UL)
#define PSR2_CH82           ((uint32_t)0x00040000UL)
#define PSR2_CH83           ((uint32_t)0x00080000UL)
#define PSR2_CH84           ((uint32_t)0x00100000UL)
#define PSR2_CH85           ((uint32_t)0x00200000UL)
#define PSR2_CH86           ((uint32_t)0x00400000UL)
#define PSR2_CH87           ((uint32_t)0x00800000UL)
#define PSR2_CH88           ((uint32_t)0x01000000UL)
#define PSR2_CH89           ((uint32_t)0x02000000UL)
#define PSR2_CH90           ((uint32_t)0x04000000UL)
#define PSR2_CH91           ((uint32_t)0x08000000UL)
#define PSR2_CH92           ((uint32_t)0x10000000UL)
#define PSR2_CH93           ((uint32_t)0x20000000UL)
#define PSR2_CH94           ((uint32_t)0x40000000UL)
#define PSR2_CH95           ((uint32_t)0x80000000UL)

/***************************************************************************
* @brief    Conversion timing registers CTR[0..2].
*           In CCFC2011BC ADC,
*           INPCMP & INPSAMP in CTR one bit more than MPC560X.
* @details  CTR0(ADC_0 /ADC_1):
*               Associated to internal precision channels (from 0 to 15).
* @details  CTR1(ADC_0):
*               Associated to internal standard channels (from 32 to 59).
* @details  CTR1(ADC_1):
*               Associated to internal standard channels (from 32 to 39).
* @details  CTR2(ADC_0):
*               Associated to external multiplexed channels (from 64 to 95).
* @note     1.ADC conversion time needs to be satisfied:
*               ADC0: Tconv > 0.9375us, ADC1: Tconv > 1.0625us.
*               ADC0: Tconv = (INPSAMP + INPCMP + INPCMP * 10) * Tadc;
*               ADC1: Tconv = (INPSAMP + INPCMP + INPCMP * 12) * Tadc;
*               Tadc = 1 / ADC_CLK;
*               ADC_CLK = SYS_CLK / CGM_SC_DC2_DIV / MCR_ADCLKSEL;
*           2.CTR_INPCMP != 0;
*           3.ADC_CLK / INPCMP <= 16MHz.
****************************************************************************/
/* Configuration bits for sampling phase duration.
 * The actual significant bits are 4 - 511. */
#define CTR_INPSAMP(n)      ((uint32_t)(n))         /* PRQA S 3472 */
#define CTR_INPSAMP_4       CTR_INPSAMP(4UL)        /* INPSAMP Min. */
#define CTR_INPSAMP_255     CTR_INPSAMP(0xFFUL)
#define CTR_INPSAMP_511     CTR_INPSAMP(0x1FFUL)    /* INPSAMP Max. */
#define CTR_INPSAMP_MASK    ((uint32_t)0x000001FFUL)
/* Configuration bits for comparison phase duration.
 * The actual significant bits are 1 - 7. */
#define CTR_INPCMP_1        ((uint32_t)0x00000200UL)
#define CTR_INPCMP_2        ((uint32_t)0x00000400UL)
#define CTR_INPCMP_3        ((uint32_t)0x00000600UL)
#define CTR_INPCMP_4        ((uint32_t)0x00000800UL)
#define CTR_INPCMP_5        ((uint32_t)0x00000A00UL)
#define CTR_INPCMP_6        ((uint32_t)0x00000C00UL)
#define CTR_INPCMP_7        ((uint32_t)0x00000E00UL)
#define CTR_INPCMP_MASK     ((uint32_t)0x00000E00UL)

/***********************************************************************************
* @brief    Normal Conversion Mask Registers 0 (NCMR[0]).
* @details  ADC_0 /ADC_1:
*           Enable bit of normal sampling for channel 0 to 15 (precision channels).
************************************************************************************/
#define NCMR0_CH0           ((uint32_t)0x00000001UL)
#define NCMR0_CH1           ((uint32_t)0x00000002UL)
#define NCMR0_CH2           ((uint32_t)0x00000004UL)
#define NCMR0_CH3           ((uint32_t)0x00000008UL)
#define NCMR0_CH4           ((uint32_t)0x00000010UL)
#define NCMR0_CH5           ((uint32_t)0x00000020UL)
#define NCMR0_CH6           ((uint32_t)0x00000040UL)
#define NCMR0_CH7           ((uint32_t)0x00000080UL)
#define NCMR0_CH8           ((uint32_t)0x00000100UL)
#define NCMR0_CH9           ((uint32_t)0x00000200UL)
#define NCMR0_CH10          ((uint32_t)0x00000400UL)
#define NCMR0_CH11          ((uint32_t)0x00000800UL)
#define NCMR0_CH12          ((uint32_t)0x00001000UL)
#define NCMR0_CH13          ((uint32_t)0x00002000UL)
#define NCMR0_CH14          ((uint32_t)0x00004000UL)
#define NCMR0_CH15          ((uint32_t)0x00008000UL)
#define NCMR0_CH0_CH15      ((uint32_t)0x0000FFFFUL)

/***********************************************************************************
* @brief    Normal Conversion Mask Registers 1 (NCMR[1]).
* @details  ADC_0:
*           Enable bit of normal sampling for channel 32 to 59 (standard channels).
* @details  ADC_1:
*           Enable bit of normal sampling for channel 32 to 39 (standard channels).
************************************************************************************/
#define NCMR1_CH32          ((uint32_t)0x00000001UL)
#define NCMR1_CH33          ((uint32_t)0x00000002UL)
#define NCMR1_CH34          ((uint32_t)0x00000004UL)
#define NCMR1_CH35          ((uint32_t)0x00000008UL)
#define NCMR1_CH36          ((uint32_t)0x00000010UL)
#define NCMR1_CH37          ((uint32_t)0x00000020UL)
#define NCMR1_CH38          ((uint32_t)0x00000040UL)
#define NCMR1_CH39          ((uint32_t)0x00000080UL)
#define NCMR1_CH32_CH39     ((uint32_t)0x000000FFUL)    /* ADC_1 End */
#define NCMR1_CH40          ((uint32_t)0x00000100UL)
#define NCMR1_CH41          ((uint32_t)0x00000200UL)
#define NCMR1_CH42          ((uint32_t)0x00000400UL)
#define NCMR1_CH43          ((uint32_t)0x00000800UL)
#define NCMR1_CH44          ((uint32_t)0x00001000UL)
#define NCMR1_CH45          ((uint32_t)0x00002000UL)
#define NCMR1_CH46          ((uint32_t)0x00004000UL)
#define NCMR1_CH47          ((uint32_t)0x00008000UL)
#define NCMR1_CH48          ((uint32_t)0x00010000UL)
#define NCMR1_CH49          ((uint32_t)0x00020000UL)
#define NCMR1_CH50          ((uint32_t)0x00040000UL)
#define NCMR1_CH51          ((uint32_t)0x00080000UL)
#define NCMR1_CH52          ((uint32_t)0x00100000UL)
#define NCMR1_CH53          ((uint32_t)0x00200000UL)
#define NCMR1_CH54          ((uint32_t)0x00400000UL)
#define NCMR1_CH55          ((uint32_t)0x00800000UL)
#define NCMR1_CH56          ((uint32_t)0x01000000UL)
#define NCMR1_CH57          ((uint32_t)0x02000000UL)
#define NCMR1_CH58          ((uint32_t)0x04000000UL)
#define NCMR1_CH59          ((uint32_t)0x08000000UL)
#define NCMR1_CH32_CH59     ((uint32_t)0x0FFFFFFFUL)    /* ADC_0 End */

/************************************************************************
* @brief    Normal Conversion Mask Registers 2 (NCMR[2]).
* @details  ADC_0:
*           Enable bit of normal sampling for channel 64 to 95
*           (external multiplexed channels).
*************************************************************************/
/* ADC_0 external[0] multiplexed channels: CH64_CH71 */
#define NCMR2_CH64          ((uint32_t)0x00000001UL)
#define NCMR2_CH65          ((uint32_t)0x00000002UL)
#define NCMR2_CH66          ((uint32_t)0x00000004UL)
#define NCMR2_CH67          ((uint32_t)0x00000008UL)
#define NCMR2_CH68          ((uint32_t)0x00000010UL)
#define NCMR2_CH69          ((uint32_t)0x00000020UL)
#define NCMR2_CH70          ((uint32_t)0x00000040UL)
#define NCMR2_CH71          ((uint32_t)0x00000080UL)
#define NCMR2_CH64_CH71     ((uint32_t)0x000000FFUL)
/* ADC_0 external[1] multiplexed channels: CH72_CH79 */
#define NCMR2_CH72          ((uint32_t)0x00000100UL)
#define NCMR2_CH73          ((uint32_t)0x00000200UL)
#define NCMR2_CH74          ((uint32_t)0x00000400UL)
#define NCMR2_CH75          ((uint32_t)0x00000800UL)
#define NCMR2_CH76          ((uint32_t)0x00001000UL)
#define NCMR2_CH77          ((uint32_t)0x00002000UL)
#define NCMR2_CH78          ((uint32_t)0x00004000UL)
#define NCMR2_CH79          ((uint32_t)0x00008000UL)
#define NCMR2_CH72_CH79     ((uint32_t)0x0000FF00UL)
/* ADC_0 external[2] multiplexed channels: CH80_CH87 */
#define NCMR2_CH80          ((uint32_t)0x00010000UL)
#define NCMR2_CH81          ((uint32_t)0x00020000UL)
#define NCMR2_CH82          ((uint32_t)0x00040000UL)
#define NCMR2_CH83          ((uint32_t)0x00080000UL)
#define NCMR2_CH84          ((uint32_t)0x00100000UL)
#define NCMR2_CH85          ((uint32_t)0x00200000UL)
#define NCMR2_CH86          ((uint32_t)0x00400000UL)
#define NCMR2_CH87          ((uint32_t)0x00800000UL)
#define NCMR2_CH80_CH87     ((uint32_t)0x00FF0000UL)
/* ADC_0 external[3] multiplexed channels: CH88_CH95 */
#define NCMR2_CH88          ((uint32_t)0x01000000UL)
#define NCMR2_CH89          ((uint32_t)0x02000000UL)
#define NCMR2_CH90          ((uint32_t)0x04000000UL)
#define NCMR2_CH91          ((uint32_t)0x08000000UL)
#define NCMR2_CH92          ((uint32_t)0x10000000UL)
#define NCMR2_CH93          ((uint32_t)0x20000000UL)
#define NCMR2_CH94          ((uint32_t)0x40000000UL)
#define NCMR2_CH95          ((uint32_t)0x80000000UL)
#define NCMR2_CH88_CH95     ((uint32_t)0xFF000000UL)
/* ADC_0 external multiplexed channels: CH64_CH95 */
#define NCMR2_CH64_CH95     ((uint32_t)0xFFFFFFFFUL)

/************************************************************************
* @brief    Injected Conversion Mask Registers 0 (JCMR[0]).
* @details  ADC_0 /ADC_1:
*               Enable bit of injected sampling for channel 0 to 15
*               (precision channels).
*************************************************************************/
#define JCMR0_CH0           ((uint32_t)0x00000001UL)
#define JCMR0_CH1           ((uint32_t)0x00000002UL)
#define JCMR0_CH2           ((uint32_t)0x00000004UL)
#define JCMR0_CH3           ((uint32_t)0x00000008UL)
#define JCMR0_CH4           ((uint32_t)0x00000010UL)
#define JCMR0_CH5           ((uint32_t)0x00000020UL)
#define JCMR0_CH6           ((uint32_t)0x00000040UL)
#define JCMR0_CH7           ((uint32_t)0x00000080UL)
#define JCMR0_CH8           ((uint32_t)0x00000100UL)
#define JCMR0_CH9           ((uint32_t)0x00000200UL)
#define JCMR0_CH10          ((uint32_t)0x00000400UL)
#define JCMR0_CH11          ((uint32_t)0x00000800UL)
#define JCMR0_CH12          ((uint32_t)0x00001000UL)
#define JCMR0_CH13          ((uint32_t)0x00002000UL)
#define JCMR0_CH14          ((uint32_t)0x00004000UL)
#define JCMR0_CH15          ((uint32_t)0x00008000UL)
#define JCMR0_CH0_CH15      ((uint32_t)0x0000FFFFUL)

/************************************************************************
* @brief    Injected Conversion Mask Registers 1 (JCMR[1]).
* @details  ADC_0:
*               Enable bit of injected sampling for channel 32 to 59
*               (standard channels).
* @details  ADC_1:
*               Enable bit of injected sampling for channel 32 to 39
*               (standard channels).
*************************************************************************/
#define JCMR1_CH32          ((uint32_t)0x00000001UL)
#define JCMR1_CH33          ((uint32_t)0x00000002UL)
#define JCMR1_CH34          ((uint32_t)0x00000004UL)
#define JCMR1_CH35          ((uint32_t)0x00000008UL)
#define JCMR1_CH36          ((uint32_t)0x00000010UL)
#define JCMR1_CH37          ((uint32_t)0x00000020UL)
#define JCMR1_CH38          ((uint32_t)0x00000040UL)
#define JCMR1_CH39          ((uint32_t)0x00000080UL)
#define JCMR1_CH32_CH39     ((uint32_t)0x000000FFUL)    /* ADC_1 End */
#define JCMR1_CH40          ((uint32_t)0x00000100UL)
#define JCMR1_CH41          ((uint32_t)0x00000200UL)
#define JCMR1_CH42          ((uint32_t)0x00000400UL)
#define JCMR1_CH43          ((uint32_t)0x00000800UL)
#define JCMR1_CH44          ((uint32_t)0x00001000UL)
#define JCMR1_CH45          ((uint32_t)0x00002000UL)
#define JCMR1_CH46          ((uint32_t)0x00004000UL)
#define JCMR1_CH47          ((uint32_t)0x00008000UL)
#define JCMR1_CH48          ((uint32_t)0x00010000UL)
#define JCMR1_CH49          ((uint32_t)0x00020000UL)
#define JCMR1_CH50          ((uint32_t)0x00040000UL)
#define JCMR1_CH51          ((uint32_t)0x00080000UL)
#define JCMR1_CH52          ((uint32_t)0x00100000UL)
#define JCMR1_CH53          ((uint32_t)0x00200000UL)
#define JCMR1_CH54          ((uint32_t)0x00400000UL)
#define JCMR1_CH55          ((uint32_t)0x00800000UL)
#define JCMR1_CH56          ((uint32_t)0x01000000UL)
#define JCMR1_CH57          ((uint32_t)0x02000000UL)
#define JCMR1_CH58          ((uint32_t)0x04000000UL)
#define JCMR1_CH59          ((uint32_t)0x08000000UL)
#define JCMR1_CH32_CH59     ((uint32_t)0x0FFFFFFFUL)    /* ADC_0 End */

/************************************************************************
* @brief    Injected Conversion Mask Registers 2 (JCMR[2]).
* @details  ADC_0:
*               Enable bit of injected sampling for channel 64 to 95
*               (external multiplexed channels).
*************************************************************************/
/* ADC_0 external[0] multiplexed channels: CH64_CH71 */
#define JCMR2_CH64          ((uint32_t)0x00000001UL)
#define JCMR2_CH65          ((uint32_t)0x00000002UL)
#define JCMR2_CH66          ((uint32_t)0x00000004UL)
#define JCMR2_CH67          ((uint32_t)0x00000008UL)
#define JCMR2_CH68          ((uint32_t)0x00000010UL)
#define JCMR2_CH69          ((uint32_t)0x00000020UL)
#define JCMR2_CH70          ((uint32_t)0x00000040UL)
#define JCMR2_CH71          ((uint32_t)0x00000080UL)
#define JCMR2_CH64_CH71     ((uint32_t)0x000000FFUL)
/* ADC_0 external[1] multiplexed channels: CH72_CH79 */
#define JCMR2_CH72          ((uint32_t)0x00000100UL)
#define JCMR2_CH73          ((uint32_t)0x00000200UL)
#define JCMR2_CH74          ((uint32_t)0x00000400UL)
#define JCMR2_CH75          ((uint32_t)0x00000800UL)
#define JCMR2_CH76          ((uint32_t)0x00001000UL)
#define JCMR2_CH77          ((uint32_t)0x00002000UL)
#define JCMR2_CH78          ((uint32_t)0x00004000UL)
#define JCMR2_CH79          ((uint32_t)0x00008000UL)
#define JCMR2_CH72_CH79     ((uint32_t)0x0000FF00UL)
/* ADC_0 external[2] multiplexed channels: CH80_CH87 */
#define JCMR2_CH80          ((uint32_t)0x00010000UL)
#define JCMR2_CH81          ((uint32_t)0x00020000UL)
#define JCMR2_CH82          ((uint32_t)0x00040000UL)
#define JCMR2_CH83          ((uint32_t)0x00080000UL)
#define JCMR2_CH84          ((uint32_t)0x00100000UL)
#define JCMR2_CH85          ((uint32_t)0x00200000UL)
#define JCMR2_CH86          ((uint32_t)0x00400000UL)
#define JCMR2_CH87          ((uint32_t)0x00800000UL)
#define JCMR2_CH80_CH87     ((uint32_t)0x00FF0000UL)
/* ADC_0 external[3] multiplexed channels: CH88_CH95 */
#define JCMR2_CH88          ((uint32_t)0x01000000UL)
#define JCMR2_CH89          ((uint32_t)0x02000000UL)
#define JCMR2_CH90          ((uint32_t)0x04000000UL)
#define JCMR2_CH91          ((uint32_t)0x08000000UL)
#define JCMR2_CH92          ((uint32_t)0x10000000UL)
#define JCMR2_CH93          ((uint32_t)0x20000000UL)
#define JCMR2_CH94          ((uint32_t)0x40000000UL)
#define JCMR2_CH95          ((uint32_t)0x80000000UL)
#define JCMR2_CH88_CH95     ((uint32_t)0xFF000000UL)
/* ADC_0 external multiplexed channels: CH64_CH95 */
#define JCMR2_CH64_CH95     ((uint32_t)0xFFFFFFFFUL)

/************************************************************************
* @brief    Decode Signals Delay Register (DSDR).
* @details  Implemented only on ADC_0.
*************************************************************************/
#define DSDR_0_CYCLE_DELAY  ((uint32_t)0x00000000UL)
#define DSDR_1_CYCLE_DELAY  ((uint32_t)0x00000002UL)
#define DSDR_2_CYCLE_DELAY  ((uint32_t)0x00000004UL)
#define DSDR_MASK           ((uint32_t)0x00000FFFUL)

/************************************************************************
* @brief    Power - down Exit Delay Register (PDEDR).
*************************************************************************/
#define PDEDR_MASK          ((uint32_t)0x000000FFUL)

/************************************************************************
* @brief    Channel Data Register (CDR[0..95]).
* @details  CDR[0..15]  = precision channels,
*           CDR[32..47] = standard channels,
*           CDR[64..95] = external multiplexed channels.
*************************************************************************/
/* CDATA[0:9], (MCR[WLSIDE] = 0)*/
#define ADC0_CDATA_MASK     ((uint32_t)0x000003FFUL)
/* CDATA[0:11], (MCR[WLSIDE] = 0)*/
#define ADC1_CDATA_MASK     ((uint32_t)0x00000FFFUL)
/* CDATA[0:9], (MCR[WLSIDE] = 1)*/
#define ADC0_CDATALEFT_MASK ((uint32_t)0x0000FFC0UL)
/* CDATA[0:11], (MCR[WLSIDE] = 1)*/
#define ADC1_CDATALEFT_MASK ((uint32_t)0x0000FFF0UL)
/* This bit reflects the mode of conversion for
 * the corresponding channel. */
#define ADC_CDR_RESULT_MASK ((uint32_t)0x00030000UL)
/* Overwrite data
 * This bit signals that the previous converted data has been
 *  overwritten by a new conversion.
 *  This functionality depends on the value of MCR[OWREN]:
 *  - When OWREN = 0, then OVERW is frozen to 0 and CDATA field
 *      is protected against being overwritten until being read.
 *  - When OWREN = 1, then OVERW flags the CDATA field
 *      overwrite status.
 *  0 Converted data has not been overwritten
 *  1 Previous converted data has been overwritten
 *      before having been read */
#define ADC_CDR_OVERW_MASK  ((uint32_t)0x00040000UL)
/* Used to notify when the data is valid
 *  (a new value has been written).
 * It is automatically cleared when data is read. */
#define ADC_CDR_VALID_MASK  ((uint32_t)0x00080000UL)

/*
* @brief    ADC_CDR_RESULT_MASK.
**/
#define CDR_RESULT_NORMAL   ((uint32_t)0x00000000UL)
#define CDR_RESULT_INJECTED ((uint32_t)0x00010000UL)
#define CDR_RESULT_CTU      ((uint32_t)0x00020000UL)
#define CDR_RESULT_RESERVED ((uint32_t)0x00030000UL)

/************************************************************************
* @brief    Channel Watchdog Select Register (CWSELR[0..11]).
* @details  ADC_0: WSEL_CHn[2:0], ADC_1: WSEL_CHn[1:0].
*************************************************************************/
#define CWSELR_THRHLR0      (0U)
#define CWSELR_THRHLR1      (1U)
#define CWSELR_THRHLR2      (2U)    /* ADC_1 End */
#define CWSELR_THRHLR3      (3U)
#define CWSELR_THRHLR4      (4U)
#define CWSELR_THRHLR5      (5U)    /* ADC_0 End */
#define ADC0_CWSELR_MASK    (0x7U)
#define ADC1_CWSELR_MASK    (0x3U)

/*===============================================================================
*                   STRUCT PROTOTYPES
*================================================================================*/
#define ADC0_SELECT         ((uint8_t)0x00U)
#define ADC1_SELECT         ((uint8_t)0x01U)

#define ADC_CTR0_CH0_CH15   ((uint8_t)0x01U)
#define ADC_CTR1_CH32_CH59  ((uint8_t)0x02U)
#define ADC_CTR2_CH64_CH95  ((uint8_t)0x04U)

struct WDG_struct/* PRQA S 3630 */
{
    uint16_t threshold_h[4];	//High threshold value 0~1023
    uint16_t threshold_l[4];	//Low threshold value 0~1023
    uint16_t wdg_select[4];		//Channel Select
    uint16_t wdg_enable[4];		//Channel Enable
};

typedef struct ADC_Config/* PRQA S 3630, 1536 */
{
    uint8_t OWREN;
    uint8_t WLSIDE;
    uint8_t MODE;
    uint8_t ADCLKSEL;
    uint8_t ACKO;
    uint8_t PWDN;
} ADC_Config;

typedef struct ADC_0_Driver/* PRQA S 1536 */
{
    const ADC_Config *config;
    volatile struct ADC0_tag *adc0_tag;
} ADC_0_Driver;

typedef struct ADC_1_Driver/* PRQA S 1536 */
{
    const ADC_Config *config;
    volatile struct ADC1_tag *adc1_tag;
} ADC_1_Driver;

typedef struct ADC_Driver/* PRQA S 3630, 1536 */
{
    uint8_t index;

    struct WDG_struct *WDG_t;
    ADC_0_Driver ADC0;
    ADC_1_Driver ADC1;
} ADC_Driver;

/*===============================================================================
*                   FUNCTION PROTOTYPES
*================================================================================*/
extern void ADC_ConfigInit(const ADC_Driver *adcd);
extern void ADC_LLD_Cfg_Init(ADC_Driver *adcd, const ADC_Config *config);
extern void ADC_LLD_ChannelConfig(const ADC_Driver *adcd, uint32_t channel);
extern void ADC_LLD_InjectedChannelConfig(const ADC_Driver *adcd, uint32_t channel);
extern void ADC_LLD_IntcConfig(const ADC_Driver *adcd, uint32_t mode);
extern void ADC_LLD_IntcEnable(const ADC_Driver *adcd, uint32_t channel);
extern uint16_t ADC_LLD_ChanValue(const ADC_Driver *adcd, uint32_t channel);
extern void ADC_LLD_ConversionTiming(const ADC_Driver *adcd, uint8_t ctrNum, uint32_t inpcmp, uint32_t inpsamp);
extern void ADC_LLD_SetClockDivide(const ADC_Driver *adcd, uint8_t clkDiv);
extern void ADC_LLD_Start(const ADC_Driver *adcd);
extern void ADC_Stop(const ADC_Driver *adcd);
extern uint8_t ADC_ECH_IntFlag(const ADC_Driver *adcd);
extern uint8_t ADC_JECH_IntFlag(const ADC_Driver *adcd);
extern void ADC_LLD_TriggerMode(const ADC_Driver *adcd, uint8_t mode);
extern void ADC_LLD_WDGInit(const ADC_Driver *adcd);
extern void ADC_LLD_CTUTriggerEnable(const ADC_Driver *adcd , uint8_t edge);
extern void ADC_LLD_InjectedStart(const ADC_Driver *adcd);
extern void ADC_LLD_DMAChannelConfig(const ADC_Driver *adcd, uint32_t channel);
extern void ADC_LLD_DMA_Enable(const ADC_Driver *adcd);
extern void ADC_LLD_CTU_Enable(const ADC_Driver *adcd);
extern uint16_t ADC_0_Receive(uint8_t Channel);

#endif  /* __ADC_LLD_H_ */

